Silicon carbide (SiC) and Gallium nitride (GaN) are wide band-gap semiconductors that will displace silicon (Si) in specialized high-voltage and high frequency applications due to their capability to achieve high voltage breakdown with low associated on-resistance, which also permits operation at higher frequencies. In addition, SiC has a thermal coefficient that is more than three times that of Si and has been operated well beyond the 120° C. limit of Si. SiC is more mature than GaN from a manufacturing/processing perspective and transistors have been demonstrated for power conditioning applications in hybrid cars, more electric aircraft, and radar power supplies.
Three types of SiC devices are reaching maturity for power conditioning applications: SiC MOSFET (metal oxide semiconductor field effect transistor), SiC VJFET (vertical junction field effect transistor), and SiC BJT (bipolar junction transistor). The SiC BJT can be used as a single normally-off switch that can directly replace Si MOSFET switches. As in MOSFET and VJFET cases, the size of the SiC BJTs is primarily limited by the defects in the SiC material. An additional problem particular to BJTs is the forward voltage degradation that is caused by the growth of stacking faults from certain basal plane dislocations within the base layer of the SiC BJT (see, e.g., Agarwal et al., Materials Science Forum Vols. 527-529 (2006), pp. 1409 to 1412). The BJT is a current controlled device and achieving high current gain in SiC BJTs is essential for power switching applications. The BJT, much like the VJFET, can operate at temperatures well above those of Si; operation at 275° C. has been reported by several groups. The BJT can be used in RF applications similar to VJFETs and SITs.
For high voltage applications above 150° C. (hybrid vehicles, more electric aircraft, power supplies, etc.), the SiC VJFET and BJT are the viable SiC candidates for power conditioning applications. The BJT has the drawback of being a current controlled device which necessitates high current gain for efficient gate drive operation. The forward voltage degradation issue also needs to be resolved. As SiC material quality improves, forward voltage degradation and high current gain will improve. With material issues resolved, the BJT might be a more cost effective solution compared to the VJFET as it is a single normally-off replacement to Si MOSFETs. Furthermore, BJTs can be used at very high voltages (beyond 3000 V) where unipolar devices like the MOSFET and VJFET are unsuitable due to the high resistivity of their drift layer.
For optimum SiC BJT performance, it is important to obtain a device breakdown voltage as close as possible to the intrinsic capability of the underlying semiconductor material. However, the breakdown voltage of practical devices is reduced by the occurrence of high electric fields at the edges of the device. In particular, electric field crowding at the edges of the device leads to premature voltage breakdown. To minimize premature voltage breakdown, specialized edge termination structures must be implemented in order to obtain maximum breakdown voltage with relatively low associated on-state resistance.
The multiple floating guard ring (MFGR) edge termination structure is used to alter the charge distribution and electric field at surfaces and material interfaces of semiconductor devices. The interface between the guard ring and the substrate in which it is embedded forms a depletion region that enhances resistance to voltage breakdown in an applied field. The MFGR also provides a cost-effective method of edge termination because it may use fewer fabrication steps than the Junction Termination Extension technique, another technique for edge termination.
There are two major drawbacks to the present state of the art fabrication approach that limit the maximum breakdown voltage that can be achieved by the BJT using MFGR.
1. By defining the rings in a distinct lithography step using customary resist-dielectric methods, breaks in the rings may occur. In particular, a break in the first ring (which commonly happens close to the corner of the MESA edge) will render the SiC device's breakdown voltage well below specification.
2. The N-doped layer surface of the BJT, inside which the guard rings are situated, is customarily covered by dielectrics (oxides) for isolation and reliability purposes. One potentially critical issue with the MFGR edge termination is that it is very sensitive to the charge at the oxide semiconductor interface. Isolation oxides in SiC devices are typically plasma deposited and the plasma processing steps may result in the incorporation of high levels of oxide charges. As a result, field oxides in SiC may be lower quality when compared to high quality thermally grown oxides. When a large amount of positive charge is present in the oxide-semiconductor interface, the surface of the lightly doped n-layer turns into n+ regions (in the semiconductor-oxide interface between the p+ rings). This results in a very high electric field at the oxide-semiconductor interface. The high electric field reduces the effectiveness of the floating guard rings and may result in reduction of blocking voltage of the devices (Yilmaz, IEEE Transactions on Electron Devices, Vol. 38. No. 7, pp. 1666-1675, 1991). In addition, this charge, mostly positive, can move toward or away from the oxide-semiconductor interface, causing time dependant breakdown voltage, or breakdown walk-out. Breakdown walk-out refers to the phenomenon where the breakdown voltage starts at a first value and degrades with time and bias. Both time dependant breakdown voltage and breakdown walk-out impact long term device reliability and are highly undesirable.
One way to overcome the surface charge sensitivity and long term reliability issues of MFGR edge terminations is to introduce Offset Field Plates on each guard ring as suggested by Yilmaz for Si power devices. Although this can be implemented relatively easily in Si, it is not practical for SiC devices due to alignment tolerance, step coverage, and oxide quality issues. In addition, introducing Offset Field Plates requires a first lithography level to pattern windows on the oxide and a second lithography level for the field plates. In field plate designs the quality of the oxide is important in achieving acceptable results as it is the oxide that supports the voltages. As mentioned before, the deposited oxides in SiC are of lower quality and accordingly, the Offset Field Plates method becomes ineffective.